1. Field of the Invention
The present invention relates to an equalization system for a signal receiver that adaptively adjusts equalization based on comparisons of samples of an equalized signal acquired both on leading and trailing edges of a sampling clock signal.
2. Description of Related Art
Binary signal can represent digital data sequences in various ways. For example, a typical non-return to zero (NRZ) transmitter transmits a signal representing a digital data sequence using a high (positive) level to represent a digital “1” data bit and a low (negative) level to represent a “0” data bit. FIG. 1 depicts an NRZ waveform VX organized into a succession of high or low voltage levels (“symbols”) wherein each symbol represents a separate bit of a data sequence, in this example the sequence {1001011001001101}. A sequence of symbols in a binary signal can represent a bit sequence in other ways. For example in a “non-return to zero inverted” (NRZI) signal each symbol corresponds to a separate bit of a data sequence, but rather than indicating the state of its corresponding bit, each symbol indicates whether its corresponding bit has the same state as a preceding bit of the sequence. A high voltage level symbol (H) indicates that the corresponding bit has the same state as its preceding bit and a low voltage level symbol (L) indicates that its corresponding bit's state differs from a preceding bit's state. Thus, an NRZI signal would represent the sequence {1001011001001101} by the symbol sequence {HLHLLLHLHLLHLHLL}.
While a transmitter may transmit a binary signal looking like signal VX, a communication channel (such as, for example a cable or a transmission line) conveying that signal to a receiver will distort the signal. A communication channel typically acts like a low-pass filter attenuating a signal's high frequency components more than its low frequency components. While transmitted signal VX departing a transmitter exhibits relatively sharp transitions between 1 and 0 symbols as illustrated in FIG. 1, the channel will smooth those sharp transitions as it delivers the signal to a receiver. Hence, a receiver might receive a signal looking for example like waveform VR of FIG. 1 rather than like the transmitted signal VX. This type of channel distortion is known as “intersymbol interference” (ISI) because states of more than one symbol can affect the voltage of the received signal VR at any given time. All NRZ, NRZI and other types digital signals are susceptible to ISI interference.
When ISI distortion is severe, a receiver would not be able to directly recover the symbol sequence represented by transmitted signal VX simply by digitizing received signal VR. A receiver should therefore include an equalization system for processing received signal VR to compensate for ISI distortion. For example, waveform X of FIG. 1 illustrates an equalized version of the received signal VR wherein the effects of ISI distortion are substantially reduced. Note that a receiver could sample compensated signal X on each leading edge of a sampling clock CLK having an appropriate phase and frequency to produce an output signal Z conveying the same symbol sequence as VX.
FIG. 2 illustrates a transmitter 6 transmitting signal VX through a channel 8 forwarding an ISI distorted version VR of the transmitted signal to a receiver 10. Receiver 10 employs a typical prior art “adaptive feed-forward” equalization system including a filter 12 for processing signal VR to produce a compensated signal X. A clock and data recovery (CDR) unit 14 periodically samples signal X to produce an output data signal Z conveying a sequence of symbols matching that of transmitted signal VX. CDR unit 14 automatically generates the sampling clock signal CLK controlling the phase and frequency with which it samples signal X and supplies both the data signal and the clock signal CLK as outputs.
Since ISI distortion occurs because the channel 8 acts like a low pass filter, filter 12 high-pass filters the VR signal to compensate for the ISI distortion. An adaptation control unit 16 supplies a control signal C to filter 12 for adjusting the filter's frequency response so that it provides an appropriate level of equalization. CDR circuit 14 generates a “jitter estimate” signal J indicating how well filter 12 compensates the VR signal for ISI distortion. As compensation improves, the average amplitude of J decreases. Adaptation control circuit 16 therefore adjusts control signal C to minimize the average magnitude of signal J, thereby optimizing the equalization provided by filter 12.
FIG. 3 illustrates CDR unit 14 of FIG. 2 in more detailed block diagram form. A latch 18 samples signal X on leading edges of the CLK signal to produce a signal Y, and a latch 20 samples signal Y on trailing edges of the CLK signal to produce the data signal Z. An XOR gate 22 receiving the X, Y signals generates a signal U, and an XOR gate 24 receiving the Y and Z signal generates a signal D. A summer 26 offsets U by D to provide a signal E representing an error in the phase of sampling clock signal CLK relative to its ideal sampling phase. A low pass filter 27 filters error signal E to supply a control voltage input VC to a voltage-controlled oscillator (VCO) 28 producing sampling clock signal CLK. Signal VC also controls a delay circuit 30 for delaying signal U by one half cycle of the CLK signal to produce a signal U′. An XOR gate 32 receiving signals U′ and D generates jitter estimate signal J.
FIG. 4 is a timing diagram illustrating behavior of various signals of CDR unit 14 of FIG. 3 when rising edges of the CLK signal arrive at latch 18 of FIG. 3 too early, ahead of the middle of symbols of signal X. Timing diagram FIG. 5 illustrates behavior of the same signals when edges of sampling clock signal CLK arrive at latch 18 too late, after the middle of symbols represented by signal X. Referring to FIGS. 4 and 5, pulses of signals U and D occur after each symbol transition in signal X, but while D signal pulses always have a 50% duty cycle, U signal pulses will have a less than 50% duty cycle when CLK signal edges occur too soon, as illustrated in FIG. 4, and will have a greater than 50% duty cycle as illustrated in FIG. 5 when sampling clock signal edges occur too late. The average voltage of error signal E, the difference between U and D signal voltages, will therefore be positive when clock signal edges arrive too soon and will be negative when clock signal edges arrive too late. Low pass filter 27 and VCO 28 adjust the sampling clock signal phase to keep the average voltage of signal E as close to zero as possible, thereby keeping the sampling clock signal phase as close as possible to ideal.
When sampling clock signal CLK has the ideal sampling phase, and signal X is perfectly equalized, rising edges of the sampling clock signal occur at the middle of signal X symbols and signals D and U′ are identical. Since signal J is the exclusive OR of signals D and U′, signal J remains continuously low. However when equalization is less than perfect, levels of signals D and U′ will differ at times, the average magnitude of jitter estimate signal J will be non-zero and it will increase with the equalization error. Adaptation control unit 16 of FIG. 2 therefore continuously monitors jitter estimate signal J and adjusts the control input C to filter 12 to set the level of filter 12 provides to minimize the average magnitude of signal J.
Although adaptation control unit 16 and filter 12 can substantially compensate for ISI distortion, channel noise and the feedback through adaptation control unit will cause signal X to exhibit some amount of jitter. FIG. 6 includes an “eye diagram” of a poorly equalized signal X showing the range of magnitudes signal X could exhibit when monitored by an oscilloscope clocked by the CLK signal. FIG. 7 illustrates a better-equalized signal X exhibiting less jitter. The average amplitude of jitter estimate signal J is proportional to the amount of jitter in signal X relative to sampling clock signal CLK.
A typical high-pass filter 12 implements the following s-domain transfer function:H(s)=(s+z)/(s+p)including a single zero z and a single pole p. Adaptation control unit 16 may adjust zero z and/or pole p to minimize jitter. For example, an adaptation control unit that adjusts only zero z will slowly increase the magnitude of z until the average magnitude of jitter estimate signal J starts to increase and then slowly decrease z until the average magnitude of J begins to increase. Such a feedback control system will cause pole z to oscillate slightly about a value that minimizes the average magnitude of jitter estimate signal J, thereby ensuring that filter 12 provides an appropriate level of equalization.
FIG. 8 illustrates a transmitter 6 transmitting a signal through a channel 8 to a prior art receiver 34 employing an “adaptive feedback” equalization system. Receiver 34 includes a summing amplifier 38 for offsetting the received signal VR by an offset signal A to produce an equalized signal X. A CDR unit 40 generates sampling clock CLK, digitizes signal X using the sampling clock as a timing reference to produce an output data signal Z and generates an error estimate signal J. An adaptation control unit 42 processes the error estimate signal J to supply a compensation control signal C to a filter 44. Filter 44 filters output signal Z with a frequency response controlled by signal C to produce the compensation signal A input to summing amplifier 38. CDR unit 40 and adaptation control circuit 42 can be similar to CDR unit 14 and adaptation control unit 16 of FIG. 2, but while filter 12 of FIG. 2 is a high pass filter, filter 44 of FIG. 8 is a low pass filter.
One drawback to the adaptive equalization systems employed by the receivers of FIGS. 2 and 8 is that the circuitry needed to generate a jitter estimate signal J can be costly. What is needed is an equalization system for a signal receiver that does not require a jitter estimate signal.